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HM5164165A Series HM5165165A Series
4194304-word x 16-bit Dynamic RAM
ADE-203-453 (Z) Preliminary Rev. 0.4 Apr. 28, 1997 Description
The Hitachi HM5164165A Series, HM5165165A Series are CMOS dynamic RAMs organized as 4,194,304word x 16-bit. They employ the most advanced CMOS technology for high performance and low power. HM5164165A Series, HM5165165A Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They have the package variations of standart 400 mil 50-pin plastic SOJ and standerd 400 mil 50-pin plastic TSOPII
Features
* Single 3.3 V (0.3 V) * Access time: 50 ns/60 ns/70 ns (max) * Power dissipation Active mode : TBD/450 mW/378 mW (max) (HM5164165A Series) : TBD/648 mW/558 mW (max) (HM5165165A Series) Standby mode : 7.2 mW (max) : 0.72 mW (max) (L-version) * EDO page mode capability * Refresh cycles RAS-only refresh 8192 cycles /64 ms (HM5164165A) 4096 cycles /64 ms (HM5165165A) /128 ms (HM5165165AL) (L-version) CBR/Hidden refresh 4096 cycles /64 ms (HM5164165A, HM5165165A) /128 ms (HM5165165AL) (L-version)
Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice.
HM5164165A Series, HM5165165A Series
* 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) * 2CAS-byte control * Battery backup operation (L-version)
Ordering Information
Type No. HM5164165AJ-5 HM5164165AJ-6 HM5164165AJ-7 HM5164165ALJ-5 HM5164165ALJ-6 HM5164165ALJ-7 HM5165165AJ-5 HM5165165AJ-6 HM5165165AJ-7 HM5165165ALJ-5 HM5165165ALJ-6 HM5165165ALJ-7 HM5164165ATT-5 HM5164165ATT-6 HM5164165ATT-7 HM5164165ALTT-5 HM5164165ALTT-6 HM5164165ALTT-7 HM5165165ATT-5 HM5165165ATT-6 HM5165165ATT-7 HM5165165ALTT-5 HM5165165ALTT-6 HM5165165ALTT-7 Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 400-mil 50-pin plastic TSOP II (TTP-50DB) Package 400-mil 50-pin plastic SOJ (CP-50DA)
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HM5164165A Series, HM5165165A Series
Pin Arrangement
HM5164165AJ/ALJSeries VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 (Top view) VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC A12 A11 A10 A9 A8 A7 A6 VSS HM5164165ATT/ALTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 (Top view) VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC A12 A11 A10 A9 A8 A7 A6 VSS
Pin Description
Pin name A0 to A12 Function Address input -- Row/Refresh address A0 to A12 -- Column address A0 to A8 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection
I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC
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HM5164165A Series, HM5165165A Series
Pin Arrangement
HM5165165AJ/ALJSeries VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 (Top view) VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 VSS HM5165165ATT/ALTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 (Top view) VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 VSS
Pin Description
Pin name A0 to A11 Function Address input -- Row/Refresh address A0 to A11 -- Column address A0 to A9 Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection
I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC
4
HM5164165A Series, HM5165165A Series
Block Diagram (HM5164165A Series)
RAS UCAS LCAS WE OE
Timing and control
A0 A1 to A8 Row decoder * * * Column address buffers
Column decoder 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array
* * *
I/O buffers
I/O0 to I/O15
Row address buffers
A9 to A12
5
HM5164165A Series, HM5165165A Series
Block Diagram (HM5165165A Series)
RAS UCAS LCAS WE OE
Timing and control
A0 A1 to A9 Row decoder * * * Column address buffers
Column decoder 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array
* * *
I/O buffers
I/O0 to I/O15
Row address buffers
A10 A11
6
HM5164165A Series, HM5165165A Series
Truth Table
RAS H L L L L L L L L L L L L L H to L H to L H to L L LCAS D L H L L H L L H L L H L H H L L L UCAS D H L L H L L H L L H L L H L H L L WE D H H H L* L* L* L* L* L*
2 2 2 2 2 2
OE D L L L D D D H H H L to H L to H L to H D D D D H
Output Open Valid Valid Valid Open Open Open Undefined Undefined Undefined Valid Valid Valid Open Open Open Open Open
Operation Standby Lower byte Read cycle Upper byte Word Lower byte Early write cycle Upper byte Word Lower byte Delayed write cycle Upper byte Word Lower byte Read-modify-write cycle Upper byte Word Word Word Word Word Read cycle (Output disabled) RAS-only refresh cycle CAS-before-RAS refresh cycle or Self refresh cycle (L-version)
H to L H to L H to L D H H H H
Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output HIZ control are done independently by each UCAS, LCAS. ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
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HM5164165A Series, HM5165165A Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 V (max)) -0.5 to +4.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Input high voltage Input low voltage Symbol VCC VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 -- -- Max 3.6 VCC + 0.3 0.8 Unit V V V Notes 1, 2 1 1
Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
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HM5164165A Series, HM5165165A Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HM5164165A Series)
HM5164165A -5 Parameter Operating current* * Standby current
1, 2
-6 Max Min TBD -- TBD --
-7 Max Min 125 2 -- -- Max Unit Test conditions 105 2 mA mA t RC = min TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH UCAS, LCAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 s t RAS 0.3 s CMOS interface RAS, UCAS, LCAS 0.2 V Dout = High-Z 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
Symbol Min I CC1 I CC2 -- --
--
TBD --
1
--
1
mA
Standby current (L-version)
I CC2
--
TBD --
TBD --
TBD A
RAS-only refresh current*2 Standby current*
1
I CC3 I CC5
-- --
TBD -- TBD --
125 5
-- --
105 5
mA mA
CAS-before-RAS refresh current
I CC6
-- -- --
TBD -- TBD -- TBD --
140 120
-- --
120 105
mA mA
EDO page mode current*1, * 3 I CC7 Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version)
4
I CC10
TBD --
TBD A
I CC11
--
TBD --
TBD --
TBD A
Input leakage current Output leakage current Output high voltage Output low voltage
I LI I LO VOH VOL
TBD TBD -10 TBD TBD -10 TBD TBD 2.4 TBD TBD 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tHPC . 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
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HM5164165A Series, HM5165165A Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) (HM5165165A Series)
HM5165165A -5 Parameter Operating current* * Standby current
1, 2
-6 Max Min TBD -- TBD --
-7 Max Min 180 2 -- -- Max Unit Test conditions 155 2 mA mA t RC = min TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH UCAS, LCAS = VIL Dout = enable t RC = min t HPC = min CMOS interface Dout = High-Z CBR refresh: tRC = 31.3 s t RAS 0.3 s CMOS interface RAS, UCAS, LCAS 0.2 V Dout = High-Z 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
Symbol Min I CC1 I CC2 -- --
--
TBD --
1
--
1
mA
Standby current (L-version)
I CC2
--
TBD --
200
--
200
A
RAS-only refresh current*2 Standby current*
1
I CC3 I CC5
-- --
TBD -- TBD --
180 5
-- --
155 5
mA mA
CAS-before-RAS refresh current
I CC6
-- -- --
TBD -- TBD -- TBD --
140 150 650
-- -- --
120 135 650
mA mA A
EDO page mode current*1, * 3 I CC7 Battery backup current* (Standby with CBR refresh) (L-version) Self refresh mode current (L-version)
4
I CC10
I CC11
--
TBD --
500
--
500
A
Input leakage current Output leakage current Output high voltage Output low voltage
I LI I LO VOH VOL
TBD TBD -10 TBD TBD -10 TBD TBD 2.4 TBD TBD 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less within one page mode cycle tHPC . 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
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HM5164165A Series, HM5165165A Series
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, UCAS and LCAS = VIH to disable Dout.
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HM5164165A Series, HM5165165A Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)*1, *2, *18, *19, *20
Test Conditions * * * * * Input rise and fall time: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5164165A/HM5165165A -5 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max -- -- -- TBD TBD -- -- -- -- TBD TBD -- -- -- -- -- -- TBD -6 Min 104 40 10 60 10 0 10 0 10 20 15 15 48 5 15 0 0 2 Max -- -- -- -7 Min 124 50 13 Max -- -- -- Unit Notes ns ns ns
10000 70 10000 13 -- -- -- -- 45 30 -- -- -- -- -- -- 50 0 10 0 13 20 15 18 58 5 18 0 0 2
10000 ns 10000 ns -- -- -- - 52 35 -- -- -- -- -- -- 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 23 22 5 6 6 7 21 21 3 4
RAS to column address delay time t RAD t RSH t CSH t CRP t OED t DZO t DZC tT
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HM5164165A Series, HM5165165A Series
Read Cycle
HM5164165A/HM5165165A -5 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time Symbol Min t RAC t CAC t AA t OEA t RCS t RCH -- -- -- -- TBD TBD TBD TBD TBD TBD TBD TBD TBD -- -- TBD TBD -- -- TBD TBD Max TBD TBD TBD TBD -- -- -- -- -- -- -- -- -- TBD TBD -- -- TBD TBD -- -- -6 Min -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- -7 Min -- -- -- -- 0 0 70 0 35 23 0 3 3 -- -- 18 3 -- -- 18 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 27 13 5 27 27 27 12 8, 9 9, 10, 17 9, 11, 17 9 21 12, 22
Read command hold time from RAS t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD
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HM5164165A Series, HM5165165A Series
Write Cycle
HM5164165A/HM5165165A -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH TBD TBD TBD TBD TBD TBD TBD Max -- -- -- -- -- -- -- -6 Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- -7 Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 23 15, 23 15, 23 14, 21 21
Read-Modify-Write Cycle
HM5164165A/HM5165165A -5 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH TBD TBD TBD TBD TBD Max -- -- -- -- -- -6 Min 149 78 33 48 15 Max -- -- -- -- -- -7 Min 175 91 39 56 18 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 14 14 14
Refresh Cycle
HM5164165A/HM5165165A -5 Parameter Symbol Min TBD TBD TBD TBD TBD Max -- -- -- -- -- CAS setup time (CBR refresh cycle) t CSR CAS hold time (CBR refresh cycle) t CHR WE setup time (CBR refresh cycle) t WRP WE hold time (CBR refresh cycle) RAS precharge to CAS hold time t WRH t RPC -6 Min 5 10 0 10 0 Max -- -- -- -- -- -7 Min 5 10 0 10 0 Max -- -- -- -- -- Unit Notes ns ns ns ns ns 21 21 22
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HM5164165A Series, HM5165165A Series
EDO Page Mode Cycle
HM5164165A/HM5165165A -5 Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge Symbol Min t HPC t RASP t CPA TBD -- -- TBD TBD TBD TBD TBD TBD TBD Max -- TBD TBD -- -- -- -- -- -- -- -6 Min 25 -- -- 35 3 10 10 35 10 10 Max -- -7 Min 30 Max -- Unit Notes ns 25 16 9, 17
100000 -- 35 -- -- -- -- -- -- -- -- 40 3 13 10 40 10 10
100000 ns 40 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns
RAS hold time from CAS precharge t CPRH Output data hold time from CAS low t DOH CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge Write pulse width during CAS precharge OE precharge time t COL t COP t RCHC t WPE t OEP
9, 17
EDO Page Mode Read-Modify-Write Cycle
HM5164165A/HM5165165A -5 Parameter Symbol Min TBD TBD Max -- -- -6 Min 68 54 Max -- -- -7 Min 79 62 Max -- -- Unit Notes ns ns 14
EDO page mode read-modify-write t HPRWC cycle time WE delay time from CAS precharge t CPW
Refresh (HM5164165A Series)
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 64 TBD Unit ms ms Note 8192 cycles 8192 cycles
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HM5164165A Series, HM5165165A Series
Refresh (HM5165165A Series)
Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 64 128 Unit ms ms Note 4096 cycles 4096 cycles
Self Refresh Mode (L-version)
HM5165165AL -5 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol Min t RASS t RPS t CHS TBD TBD TBD Max -- -- -- -6 Min 100 110 -50 Max -- -- -- -7 Min 100 130 -50 Max -- -- -- Unit Notes s ns ns
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, than the access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles.
16
HM5164165A Series, HM5165165A Series
16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 19 All the V CC and VSS pins shall be supplied with the same voltages. 20. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 21. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 22. t CRP, t CHR, t RCH, t CPA and tCPW are determined by the later rising edge of UCAS or LCAS. 23. t CWL, t DH, t DS and t CSH should be satisfied by both UCAS and LCAS. 24. t CP is determined by the time that both UCAS and LCAS are high. 25. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value.The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and t OH, and between tOFR and t OFF. 28. Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS 100 s, then RAS precharge time should use t RPS instead of tRP. 29. CBR burst refresh or 4096 cycles of distributed CBR refresh with 15.6 s interval should be executed within 64 ms immediately after exiting from and before entering into the self refresh mode. 30. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 31. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL.
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HM5164165A Series, HM5165165A Series
Notes concerning 2CAS control
Please do not separate the UCAS/LCAS operation timing intentionally. UCAS/LCAS are allowed under the following conditions. However skew between
1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS Delayed write UCAS Early write LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP tUL) is satisfied, EDO page mode can be performed.
RAS
UCAS
LCAS t UL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
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HM5164165A Series, HM5165165A Series
Timing Waveforms*31
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
UCAS LCAS
t ASR t RAD t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
WE t WED t DZC t CDD t RDD Din High-Z
t DZO
t OEA
t OED
OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout
t CAC t AA t RAC t CLZ
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HM5164165A Series, HM5165165A Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT UCAS LCAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
20
HM5164165A Series, HM5165165A Series
Delayed Write Cycle*20
t RC t RAS
t RP
RAS t CSH t RCD tT UCAS LCAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED t OEP
t DZO

OE t OEZ t CLZ Dout High-Z Invalid Dout 21
HM5164165A Series, HM5165165A Series
Read-Modify-Write Cycle*20
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
UCAS LCAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA t OEP
t OEH
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
22
HM5164165A Series, HM5165165A Series
RAS-Only Refresh Cycle
t RC t RAS RAS tT t CRP t RPC t CRP t RP
UCAS LCAS
t ASR Address t OFR t OFF Dout High-Z Row t RAH
23
HM5164165A Series, HM5165165A Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS t RP t RAS t RC t RP
RAS tT t RPC t CP UCAS LCAS t WRP t WRH WE t WRP t WRH t CSR t CHR t RPC t CP t CRP t CSR t CHR
Address t OFR t OFF Dout High-Z
24
HM5164165A Series, HM5165165A Series
Hidden Refresh Cycle
t RC t RAS t RC t RAS t RC t RP t RAS t RP
t RP
RAS tT t RSH t RCD
UCAS LCAS
t CHR
t CRP
t RAD t ASR t RAH Address Row t ASC
t RAL t CAH
Column
t RCS WE
t RRH t RCH
t DZC High-Z Din
t WED t CDD t RDD
t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout t OFR t OHR
t OED
t OFF t OH
t OEZ t WEZ t OHO
25
HM5164165A Series, HM5165165A Series
EDO Page Mode Read Cycle
t RP
RAS
t RASP tT t CSH t CAS t RCS t RCHR t RCH t CP t HPC t CAS t CP t HPC tCAS t RCHC
t HPC t CPRH t CP t t CRP
RSH
UCAS LCAS
tCAS t RRH t RCH
WE
tASR
Address
tRAH tASC Row
tCAH
t WPE t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL tOEP tCOP tOEP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tWEZ
tOHO
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ
tCAC
tRAC
tOEA
tDOH
tOHO
tOEA
tOHO tOFF tOH
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
26
HM5164165A Series, HM5165165A Series
EDO Page Mode Read Cycle (2CAS)
t RP
RAS
t RASP t HPC t CAS tHPC
t CP
tT
LCAS
t CSH t CAS
t CP
t CP
t HPC tRSH tCAS
t CRP
UCAS
t CAS t RCHC t RCS t RRH t RCH
WE
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL
tDZC
t CAL
tRDD tCDD
Din
High-Z tDZO tOEP tCOL tOEP tCOP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tAA
tOHO
tOEZ
tOFR tOHR tOEZ tOHO tOFF tOH
tRAC
tDOH
tOEA
tCAC
tOHO
L Dout
Dout 1
Dout 2
Dout 2
Dout 4
tCPA tAA tCAC
tOEA
U Dout
Dout 1
Dout 3
Dout 4
27
HM5164165A Series, HM5165165A Series
EDO Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS UCAS LCAS t CP t HPC t CAS t CP t RSH t CAS t CRP
t ASR t RAH
t ASC
t CAH
t ASC
tCAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z* * t WCS t WCS (min)
28
HM5164165A Series, HM5165165A Series
EDO Page Mode Delayed Write Cycle*20
t RASP t RP RAS tT t CSH t RCD
UCAS LCAS
t CP t CAS t HPC t CAS
t CP t RSH t CAS
t CRP
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t OEP t WP t DZC t DS t DH Din 2 t DZO t OED t OEP t OEP t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
Invalid Dout Invalid Dout Invalid Dout
29
HM5164165A Series, HM5165165A Series
EDO Page Mode Read-Modify-Write Cycle*20
t RASP t RP RAS tT t CP t RCD
UCAS LCAS
t HPRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO
t OED
t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t WP t DZC t DS t DH Din 2 t OED t OEP t OEH t DZO t OED
t WP t DZC t DS t DH Din N t OEP t OEH
Din 1 t OEP t OEH t DZO
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
30
HM5164165A Series, HM5165165A Series
EDO Page Mode Mix Cycle (1)
t RP
RAS
t RASP t CRP tCAS tRSH t RCS tCPW tAWD t ASC tRAH Row tCAH t ASC t CAH Column 2 t CAL t DS t DH Din 1 High-Z tOED tOEP tWED t DS t DH Din 3 tASC t CAH Column 3 tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS t RRH t RCH
tT
UCAS LCAS
t CP t CAS t CSH t RCD t WCS t WCH t CAS
t CP
t CP tCAS
WE
tASR
Address
tASC
Column 1
Din

tCPA tAA tOEA tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH tCAC t DOH tCAC t OHO tOEA
Dout
OE
Dout 2
Dout 3
Dout 4
31
HM5164165A Series, HM5165165A Series
EDO Page Mode Mix Cycle (2)
t RP
RAS
t RASP
tT
UCAS LCAS
t CSH t CAS t RCD t RCS t RCHR
t CP t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOEP tOED tCOP tRSH
t CRP
t RCH tWCS t WCH
t RCS
t RRH t RCH
WE
tASR
Address
tRAH Row
t ASC
tCAH
t ASC t CAH Column 2
t ASC t CAH Column 3 t CAL
Column 1 t CAL
t DS
Din
t DH Din 2 tOEP
tRDD tCDD
High-Z
tOED
OE
tWED
tCOL t OEA tOEZ t OHO tCPA tAA tCAC tOEZ t OHO
Dout 3
tAA tOEA tCAC tRAC
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout
Dout 1
32
HM5164165A Series, HM5165165A Series
Self Refresh Cycle (L-version)* 28, 29, 30
t RASS
t RP
t RPS
RAS t RPC tT t CRP t CHS
, ,
t CP t CSR UCAS LCAS t WRP WE t OFR t OFF Dout
t WRH
, + & $
High-Z 33
HM5164165A Series, HM5165165A Series
Package Dimensions
HM5164165AJ/ALJ Series HM5165165AJ/ALJ Series (CP-50DA)
Unit: mm
50
20.95 21.38 Max
26 10.16 0.13 11.18 0.13
1
0.47
25 3.50 0.26 0.90 0.26 2.55 0.46 9.40 0.25
Hitachi Code JEDEC Code EIAJ Code Weight CP-50DA MO-165-BA -- 1.2 g
1.09 Max
0.32 +0.08 -0.07 0.31 0.04
0.80 0.10
34
HM5164165A Series, HM5165165A Series
HM5164165ATT/ALTT Series HM5165165ATT/ALTT Series (TTP-50DB)
Unit: mm
20.95 21.35 Max 50 26
1 0.32
+0.08 -0.07
0.80 0.16
M
25
10.16
11.76 0.20 0 - 5 0.68 0.5 0.1
0.10 1.075 Max
0.145 -0.02
0.08 Min 0.18 Max
1.2 Max
+0.03
35
HM5164165A Series, HM5165165A Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
36
HM5164165A Series, HM5165165A Series
Revision Record
Rev. 0.0 0.1 Date Apr. 20, 1996 Apr. 26, 1996 Contents of Modification Initial issue Change format Unification of HM5164165A Series and HM5165165A Series Addition of HM5164165A/HM5165165A-5 Series Addition of HM5164165AJ/ALJ Series, HM5165165AJ/ALJ Series (CP-50DA) Pin Descriptions Addition of Row/Refresh address and Column address to address input Addition of Block Diagrams DC Characteristics (HM5164165A) I CC1 max: 110/100 mA to TBD/140/130 mA I CC3 max: 110/100 mA to TBD/140/120 mA I CC6 max: 130/115 mA to TBD/150/130 mA I CC7 max: 130/115 mA to TBD/150/130 mA Addition of note 4 AC Characteristics t RCD max: 38/45 ns to TBD/45/52 ns t COP min: 5/5 ns to TBD/10/10 ns Addition of t WPE and tOEP Addition of notes 28 to 30 Change of notes 3 and 13 Timing waveforms Addition of t WPE and tOEP timings Deletion of note: t OEH tCWL 0.2 Jun. 12, 1996 AC Characteristics Change of notes 20 and 31 Timing waveforms Deletion of notes about undefined pins 0.3 Jan. 22, 1997 Power dissipation TBD/540/468 mW to TBD/450/378 mW (max) (HM5164165A Series) TBD/684/612 mW to TBD/648/558 mW (max) (HM5165165A Series) DC Characteristics (HM5164165A Series) I CC1(max): TBD/140/120 mA to TBD/125/105 mA I CC3(max): TBD/140/120 mA to TBD/125/105 mA I CC6(max): TBD/150/130 mA to TBD/140/120 mA I CC7(max): TBD/150/130 mA to TBD/120/105 mA I LO test conditions: 0 V Vout VCC + 0.3 to 0 V Vout VCC J. Kitano J. Kitano S. Ikenaga J. Kitano Drawn by S. Ikenaga S. Ikenaga Approved by J. Kitano J. Kitano
37
HM5164165A Series, HM5165165A Series
Revision Record (cont)
Rev. 0.3 Date Jan. 22, 1997 Contents of Modification DC Characteristics (HM5165165A Series) I CC1(max): TBD/190/170 mA to TBD/180/155 mA I CC3(max): TBD/190/170 mA to TBD/180/155 mA I CC6(max): TBD/150/130 mA to TBD/140/120 mA I CC7(max): TBD/150/130 mA to TBD/150/135 mA I LO test conditions: 0 V Vout VCC + 0.3 to 0 V Vout VCC 0.4 Apr. 28, 1997 Power dissipation Stanby mode (L-version): TBD to 0.72 mW(max) DC Characteristics (HM5165165A Series) I CC2(max)(L-version): TBD/TBD/TBD A to TBD/200/200 A I CC10(max): TBD/TBD/TBD A to TBD/650/650 A I CC11(max): TBD/TBD/TBD A to TBD/500/500 A Correct errors (HM5164165A Series) t REF (L-version): 128 ms to TBD (for susupention of L-version), 4096 cycyles to 8192 cycles Drawn by Approved by
38

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